Title:
Digital logic design : a rigorous approach
Author:
Even, Guy.
ISBN:
9781107027534
Personal Author:
Publication Information:
New York : Cambridge University Press, 2012.
Physical Description:
xx, 348 pages : illustrations ; 26 cm.
Contents:
Machine generated contents note: pt. I PRELIMINARIES -- 1.Sets and Functions -- 1.1.Sets -- 1.2.Relations and Functions -- 1.3.Boolean Functions -- 1.4.Commutative and Associative Binary Operations -- 2.Induction and Recursion -- 2.1.Induction -- 2.2.Recursion -- 2.3.Application: One-to-One and Onto Functions -- 3.Sequences and Series -- 3.1.Sequences -- 3.2.Series -- 4.Directed Graphs -- 4.1.Definitions -- 4.2.Topological Ordering -- 4.3.Longest Path in a DAG -- 4.4.Rooted Trees -- 5.Binary Representation -- 5.1.Division and Modulo -- 5.2.Bits and Strings -- 5.3.Bit Ordering -- 5.4.Binary Representation -- 5.5.Computing a Binary Representation -- 5.6.More on Unique Binary Representation -- 6.Propositional Logic -- 6.1.Boolean Formulas -- 6.2.Truth Assignments -- 6.3.Satisfiability and Logical Equivalence -- 6.4.Interpreting a Boolean Formula as a Function -- 6.5.Substitution -- 6.6.Complete Sets of Connectives -- 6.7.Important Tautologies -- 6.8.De Morgan's Laws --
Contents note continued: 7.Asymptotics -- 7.1.Order of Growth Rates -- 7.2.Recurrence Equations -- 8.Computer Stories: Big Endian versus Little Endian -- pt. II COMBINATIONAL CIRCUITS -- 9.Representations of Boolean Functions by Formulas -- 9.1.Sum of Products -- 9.2.Product of Sums -- 9.3.The Finite Field GF(2) -- 9.4.Satisfiability -- 9.5.Relation to P versus NP -- 9.6.Minimization Heuristics -- 10.The Digital Abstraction -- 10.1.Transistors -- 10.2.A CMOS Inverter -- 10.3.From Analog Signals to Digital Signals -- 10.4.Transfer Functions of Gates -- 10.5.The Bounded-Noise Model -- 10.6.The Digital Abstraction in the Presence of Noise -- 10.7.Stable Signals -- 10.8.Summary -- 11.Foundations of Combinational Circuits -- 11.1.Combinational Gates: An Analog Approach -- 11.2.Back to the Digital World -- 11.3.Combinational Gates -- 11.4.Wires and Nets -- 11.5.Combinational Circuits -- 11.6.Properties of Combinational Circuits -- 11.7.Simulation and Delay Analysis --
Contents note continued: 11.8.Completeness -- 11.9.Cost and Propagation Delay -- 11.10.Example: Relative Gate Costs and Delay -- 11.11.Semantics and Syntax -- 11.12.Summary -- 12.Trees -- 12.1.Associative Boolean Functions -- 12.2.Trees of Associative Boolean Gates -- 12.3.Optimality of Trees -- 12.4.Summary -- 13.Decoders and Encoders -- 13.1.Buses -- 13.2.Decoders -- 13.3.Encoders -- 13.4.Summary -- 14.Selectors and Shifters -- 14.1.Multiplexers -- 14.2.Cyclic Shifters -- 14.3.Logical Shifters -- 14.4.Arithmetic Shifters -- 14.5.Summary -- 15.Addition -- 15.1.Definition of a Binary Adder -- 15.2.Ripple Carry Adder -- 15.3.Lower Bounds -- 15.4.Conditional Sum Adder -- 15.5.Compound Adder -- 15.6.Reductions between Sum and Carry Bits -- 15.7.Redundant and Nonredundant Representation -- 15.8.Summary -- 16.Signed Addition -- 16.1.Representation of Negative Integers -- 16.2.Computing a Two's Complement Representation -- 16.3.Negation in Two's Complement Representation --
Contents note continued: 16.4.Properties of Two's Complement Representation -- 16.5.Reduction: Two's Complement Addition to Binary Addition -- 16.6.A Two's-Complement Adder -- 16.7.A Two's Complement Adder/Subtractor -- 16.8.Summary -- pt. III SYNCHRONOUS CIRCUITS -- 17.Flip-Flops -- 17.1.The Clock -- 17.2.Edge-Triggered Flip-Flop -- 17.3.Arbitration -- 17.4.Arbiters: An Impossibility Result -- 17.5.Necessity of Critical Segments -- 17.6.A Timing Example -- 17.7.Bounding Instability -- 17.8.Other Types of Memory Devices -- 17.9.Summary -- 18.Memory Modules -- 18.1.The Zero Delay Model -- 18.2.Registers -- 18.3.Random Access Memory (RAM) -- 18.4.Read-Only Memory (ROM) -- 18.5.Summary -- 19.Foundations of Synchronous Circuits -- 19.1.Definition -- 19.2.The Canonic Form of a Synchronous Circuit -- 19.3.Timing Analysis: The Canonic Form -- 19.4.Functionality: The Canonic Form -- 19.5.Finite State Machines -- 19.6.Timing Analysis: The General Case --
Contents note continued: 19.7.Simulation of Synchronous Circuits -- 19.8.Synthesis and Analysis -- 19.9.Summary -- 20.Synchronous Modules: Analysis and Synthesis -- 20.1.Example: A Two-State FSM -- 20.2.Sequential Adder -- 20.3.Initialization and the Corresponding FSM -- 20.4.Counter -- 20.5.Revisiting Shift Registers -- 20.6.Revisiting RAM -- pt. IV A SIMPLIFIED DLX -- 21.The ISA of a Simplified DLX -- 21.1.Why Use Abstractions? -- 21.2.Instruction Set Architecture -- 21.3.Examples of Program Segments -- 21.4.Summary -- 22.A Simplified DLX: Implementation -- 22.1.Datapath -- 22.2.Control -- 22.3.RTL Instructions -- 22.4.Examples of Instruction Execution -- 22.5.Summary.
Abstract:
"Chapter 1 Sets and Functions This chapter introduces two major notions: sets and functions. We are all familiar with real functions, for example f(x} = 2x + 1 and g(x} = sin(x). Here the approach is somewhat different. The first difference is that we do not limit the discussion to the set of real numbers. Instead, we consider arbitrary sets, and are mostly interested in sets that contain only a finite number of elements. The second difference is that we do not define a 'rule" for assigning a value for each x. Instead, a function is simply a list of pairs (x,y), where y denotes the value of the function when the argument equals x. The definition of functions relies on the definitions of sets and relations over sets. That is why we need to define various operations over sets such as: union, intersection, complement, and Cartesian product. The focus of this book is Boolean functions. Boolean functions are a special family of functions. Their arguments and values are finite sequences of zero and ones (also called bits). In this chapter we show how to represent a Boolean function by a truth table and multiplication tables. Other representations presented later in the book are: Boolean formulas and combinational circuits"--
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