Introduction -- Mixed-Signal Circuits and Systems -- Different Processors: Electrical to Mechanical -- Analog versus Digital Processors -- Analog, Digital, Mixed-Signal Circuits and Systems -- Two Types of Mixed-Signal Systems -- Nanoscale CMOS Circuit Technology -- Developmental Trend -- Nanoscale CMOS Alternative Device Options -- Advantages and Disadvantages of Technology Scaling -- Challenges in Nanoscale Design -- Power Consumption and Leakage Dissipation Issues in AMS-SoCs -- Power Consumption in Various Components in AMS-SoCs -- Power and Leakage Trend in Nanoscale Technology -- The Impact of Power Consumption and Leakage Dissipation -- Parasitics Issue -- Types of Parasitics -- The Impact of Parasitics -- Challenges to Account Parasitics during Design -- Nanoscale Circuit Process Variation Issues -- Types of Process Variation

The Impact of Process Variation -- The Temperature Variation Issue -- The Issue of Temperature -- The Impact of Temperature -- Challenges to Account through PVT-Aware Design -- Challenges in Nanoscale CMOS AMS-SoC Design -- AMS-SoC Design Flow -- AMS-SoC Unified Optimization -- Tools for Mixed-Signal Circuit Design -- The AMS-SoC Design Issue -- Languages for AMS-SoC Design -- Tools for AMS-SoC Design and Simulation -- Transistor Models -- Questions -- References -- Introduction -- Atomic Force Microscope -- What Is It? -- Background -- What Is Inside? -- Biosensor Systems -- What Is It? -- Background -- What Is Inside? -- Blu-Ray Player -- What Is It? -- Home Video Systems Background: From Video Cassette Player to Blu-Ray Player -- What Is Inside? -- Drug-Delivery Nano-Electro-Mechanical Systems -- What Is It? -- Background -- What Is Inside?

Digital Video Recorder -- What Is It? -- Background -- What Is Inside? -- AV-MATtroencephalogram System -- What Is It? -- Background -- What Is Inside? -- GPS Navigation Device -- What Is It? -- Background -- What Is Inside? -- GPU-CPU Hybrid System -- What Is It? -- Background -- What Is Inside? -- Networked Media Tank -- What Is It? -- Background -- What Is Inside? -- Net-Centric Multimedia Processor -- What Is It? -- Background -- What Is Inside? -- Radiation Detection System -- What Is It? -- Background -- What Is Inside? -- Radio Frequency Identification Chip -- What Is It? -- Background -- What Is Inside? -- Secure Digital Camera -- What Is It? -- Background -- What Is Inside? -- Set-Top Box -- What Is It? -- Background -- What Is Inside?

Hot Carrier Injection -- Negative Bias Temperature Instability -- Latchup Effect -- Time-Dependent Dielectric Breakdown -- AV-MATtromigration -- Thermal Stress -- The Trust Issue -- Information Protection Issue -- Information Leakage Issue -- Chip Intellectual Property Protection Issue -- Malicious Design Modifications Issue -- Questions -- References -- Introduction -- Phase-Locked Loop System Types -- Phase-Locked Loop System: A Broad Overview -- Definition -- Block-Level Representation -- Characteristics, or Performance Metrics -- Theory in Brief -- Oscillator Circuits -- Oscillator Types -- Oscillator Characteristics, or Performance Metrics -- Comparison of Oscillators -- Ring Oscillators -- Basics -- 45-nm CMOS -- Multigate FET -- Carbon Nanotube -- Current-Starved Voltage Controlled Oscillators

Basics -- Circuit Design -- 90-nm CMOS -- 50-nm CMOS -- 45-nm CMOS -- 45-nm Double-Gate FinFET -- LC-Tank Voltage-Controlled Oscillator -- Basics -- 180-nm CMOS -- CNTFET -- Memristor -- Relaxation Oscillators -- Low-Power Relaxation Oscillator -- Memristor Relaxation Oscillator -- Memristor-Based Schmitt Trigger Oscillator -- Phase-Frequency Detectors -- D Flip-Flop-Based PFD -- XOR Gate-Based PFD -- Charge Pumps -- Basics -- 180-nm CMOS -- Loop Filters -- Frequency Dividers -- Basics -- DFF-Based 180-nm CMOS -- JK Flip-Flop-Based 45-nm CMOS -- Design and Characterization of a 180-nm CMOS PLL -- All Digital Phase-Locked Loop -- Basics -- A Simple ADPLL Using an NCO -- A High-Resolution ADPLL Using Double DCO -- Delay-Locked Loop -- Basics -- An Analog DLL for Variable Frequency Generation

A Digital DLL -- Questions -- References -- Introduction -- Types of Electronic Signal Converters -- Concrete Applications -- Signal Converter Types -- Selected ADC Architectures: Brief Overview -- Overview -- Ramp-Compare ADC or Ramp Run-Up ADC -- Flash ADC or Direct Conversion ADC -- Successive-Approximation ADC -- Integrating ADC -- Pipeline ADC or Subranging ADC -- Sigma-Delta ADC or Oversampling ADC -- Time-Interleaved ADC -- Folding ADC -- Tracking ADC or Counter-Ramp ADC or Delta-Encoded ADC -- Architecture Selection -- Selected DAC Architectures: Brief Overview -- Binary-Weighted DAC -- Thermometer-Coded DAC -- Pulse-Width Modulator DAC -- R-2R Ladder DAC -- Segmented DAC -- Oversampling or Interpolating DAC -- Sigma-Delta DAC -- Successive-Approximation or Cyclic or Algorithmic DAC -- Multiplying DAC -- Pipeline DAC -- Characteristics for Data Converters

Characteristics for ADC -- Characteristics for DAC -- A 90-nm CMOS-Based Flash ADC -- Comparator Bank -- 1 of N Code Generator -- NOR ROM -- Physical Design and Characterization of 90-nm ADC -- Post-Layout Simulation and Characterization -- A 45-nm CMOS-Based Flash ADC -- Comparator Bank -- 1 of N Code Generator -- NOR ROM -- Functional Simulation and Characterization -- Single-Electron-Based ADC -- Single-Electron Circuitry-Based ADC -- Single-Electron Transistor-Based ADC -- Organic Thin-Film Transistor-Based ADCs -- Organic Thin-Film Transistor VCO-Based ADC -- Complementary Organic Thin-Film Transistor-Based Successive-Approximation ADC -- Sigma-Delta Modulator-Based ADC

Characteristics of the Image Sensors -- A Concrete Example: 32-nm CMOS APS Design -- Smart Image Sensors -- Secure Image Sensors -- Nanoelectronics-Based Gas Sensors -- CNTFET-Based Gas Sensor -- CNTFET-Based Chemical Sensor -- Body Sensors -- Epileptic Seizure Sensors -- Humidity Sensors -- A Diode-Based Humidity Sensor -- A CMOS Device[ -- ]Based Humidity Sensor -- Motion Sensors -- Sense Amplifiers -- Types of Sense Amplifiers -- Performance Metrics for the Sense Amplifiers -- A Concrete Example: 45-nm CMOS Clamped Bitline Sense Amplifier -- Questions -- References -- Introduction -- Static Random-Access Memory -- SRAM Array -- Different Types of SRAM -- Traditional Six-Transistor SRAM -- Four-Transistor SRAM -- Five-Transistor SRAM -- Seven-Transistor SRAM -- Eight-Transistor SRAM -- Nine-Transistor SRAM -- Ten-Transistor SRAM

Performance Metrics of SRAM -- Characterization of Specific SRAMs -- Dynamic Random-Access Memory -- DRAM Array -- Different Types of DRAM -- Selected DRAM Designs Based on Topology -- DRAMs Based on Modes of Operation -- Synchronous DRAMs -- Video or Graphics DRAM -- Ferroelectric DRAM -- Characteristics of DRAM -- Twin-Transistor Random-Access Memory -- Thyristor Random-Access Memory -- Read-Only Memory -- Programmable Read-Only Memory -- Erasable Programmable Read-Only Memory -- AV-MATtrically Erasable Programmable Read-Only Memory -- Flash Memory -- Resistive Random-Access Memory -- Nonvolatile Resistive RAM for Storage -- Conductive Metal-Oxide Memory -- Memristor-Based Nonvolatile SRAM -- Magnetic or Magnetoresistive Random-Access Memory -- Phase-Change RAM -- Questions -- References -- Introduction -- AMS-SoC: A Complete Design Perspective -- Integrated Circuit Design Flow: Top-Down versus Bottom-Up

Analog Circuit Design Flow -- Behavioral Simulation -- Transistor-Level Design or Schematic Capture -- Transistor-Level Simulation and Characterization -- Physical Design or Layout Design -- Design Rule Check -- Parasitic (RCLK) Extraction -- Layout versus Schematic Verification -- AV-MATtrical Rule Check -- Physical Design Characterization -- Variability Analysis -- Performance Optimization -- Digital Circuit Design Flow -- System-Level Design -- Architecture-Level Design -- Logic-Level Design -- Transistor-Level Design -- Physical Design -- Physical Verification -- Design Signoff -- Engineering Change Order -- Circuit Fabrication, Packaging, and Testing -- Analog and Mixed-Signal Circuit Design Flow -- Mixed-Signal Design Flow -- Analog and/or Mixed-Signal Circuit Synthesis Techniques -- Design Flow Using Commercial Electronic Design Automation Tools -- Selected Commercial EDA Tools -- For Analog Design

For Digital Design -- For Mixed-Signal System Design -- Design Flow Using Free or Open-Source EDA Tools -- Selected Free or Open-Source EDA Tools -- For Analog Design -- For Digital Design -- For Mixed-Signal Design -- Comprehensive Design Flows -- For Analog/Mixed-Signal Circuits and Systems -- For Digital Circuits and Systems -- Process Design Kit and Libraries -- EDA Tool Installation -- Client-Server Platform -- Workstation-Based Platform -- Mixed-Configuration Platform -- Questions -- References -- Introduction -- Simulation Types and Languages for Circuits and Systems -- Simulations Based on Abstraction Levels -- Simulations Based on Signal Types -- Simulations Based on System Models -- Simulations Based on Design Tasks -- Simulation Languages -- Behavioral Simulation using MATLAB® -- System- or Architecture-Level Simulations -- Circuit-Level Simulations

Device-Level Simulations -- Simulink®- or Simscape®-Based Simulations -- System- or Architecture-Level Simulations -- Circuit-Level Simulations -- Device-Level Simulations -- Circuit-Level and/or Device-Level Analog Simulations -- SPICE Analog Simulation Background -- Commercial Accurate Analog Circuit Simulators -- Free and/or Open-Source Accurate SPICE -- Fast SPICE -- Analog-Fast SPICE -- High-Speed SPICE -- Different Types of Analysis using SPICE -- SPICE-Based Simulation Examples -- Inside of SPICE -- SPICE Simulation Flow -- Verilog-A-Based Analog Simulation -- Verilog-A-Based Circuit-Level Simulations -- Verilog-A-Based Device-Level Simulations -- Simulations of Digital Circuits or Systems -- SystemVerilog-Based Simulation -- VHDL-Based Simulation -- MyHDL-Based Simulation -- SystemC-Based Simulation -- Mixed-Signal HDL-Based Simulation -- Verilog-AMS-Based Simulation

Digital SoC Power or Energy Optimization Procedures: An Overview -- Presilicon Power Reduction Techniques -- Brief Discussion -- Dual-Threshold-Based Circuit-Level Optimization of a Universal Level Converter -- Dual-Oxide-Based Logic-Level Optimization of Digital Circuits -- Dual-Oxide-Based RTL Optimization of Digital Circuits -- Hardware-Based Postsilicon Power Reduction Techniques -- Brief Discussion -- Dynamic or Variable Frequency Clocking for Power Reduction -- Adaptive Voltage Scaling for Power and Energy Reduction -- Dynamic Power Reduction Techniques -- Brief Discussion -- Dual-Voltage and Dual-Frequency-Based Circuit-Level Technique -- Multiple Supply Voltage-Based RTL Technique -- Subthreshold Leakage Reduction Techniques -- Brief Discussion -- Dual-Threshold-Based Circuit-Level Optimization of Nano-CMOS SRAM -- Gate-Oxide Leakage Reduction Techniques -- Brief Discussion -- Dual-Oxide-Based Circuit-Level Optimization of a Current-Starved VCO

Dual-Oxide-Based RTL Optimization of Digital ICs -- Parasitics: Brief Overview -- The Effects of Parasitics on Integrated Circuits -- Parasitics in Real-Life Example Circuits -- Effects of the Parasitics -- Modeling and Extraction of Parasitics -- Signal Propagation: In a Real Wire -- Parasitics Modeling and Simulation: The Key Aspects -- Circuit (Device+Parasitic) Extraction Process -- Parasitics Extraction Techniques -- Parasitics Modeling -- Parasitics Model Order Reduction -- Design Flows for Parasitic-Aware Circuit Optimization -- Parasitic-Aware Analog Design Flow with Multilevel Optimizations

Hardware-Based Thermal Monitoring -- Software-Based Temperature Monitoring -- Hybrid Hardware- and Software-Based Thermal Monitoring -- Temperature Control or Management -- Basic Principle -- Types -- Thermal-Aware Circuit Optimization -- A Thermal-Aware SRAM Optimization -- A Thermal-Aware VCO Optimization -- Thermal-Aware Digital Design Flows -- Thermal-Aware Digital Synthesis -- Thermal-Aware Physical Design -- Thermal-Aware Register-Transfer-Level Optimization -- Thermal-Aware System-Level Design -- Questions -- References -- Introduction -- Methods for Variability Analysis -- Monte Carlo Method -- Design of Experiments Method -- Corner-Based Method -- Fast Monte Carlo Methods -- Tool Setup for Statistical Analysis

Methods for Variability-Aware Design Optimization -- Brief Concept -- Variability-Aware Schematic Design Optimization Flow -- Single Manual Layout Iteration Automatic Flow for Variability-Aware Optimization -- Variability-Aware Design of Active Pixel Sensor -- Impact of Variability on APS Performance Metrics -- Variability-Aware APS Optimization -- Variability-Aware Design of Nanoscale VCO Circuits -- A Conjugate-Gradient-Based Optimization of a 90-nm CMOS Current-Starved VCO -- A Particle Swarm Optimization Approach for a 90-nm Current-Starved VCO -- Process Variation Tolerant LC-VCO Design -- Variability-Aware Design of the SRAM -- Register-Transfer-Level Methods for Variability-Aware Digital Circuits -- Brief Overview -- A Simulated-Annealing-Based Statistical Approach for RTL Optimization

A Taylor-Series Expansions Diagram-Based Approach for RTL Optimization -- Variability-Aware RTL Timing Optimization -- RTL Postsilicon Techniques for Variability Tolerance -- System-Level Methods for Variability-Aware Digital Design -- An Adaptive Body Bias Method for Dynamic Process Variation Compensation -- Parametric Variation Effect Mitigation in Clock Networks -- Statistical Methods for Yield Analysis -- Questions -- References -- Introduction -- Metamodel: An Overview -- Concept -- Types -- Generation Flow -- Metamodel versus Macromodel -- Metamodel-Based Ultrafast Design Flow -- Polynomial-Based Metamodeling -- Theory -- Generation -- Ring Oscillator -- LC-VCO -- Verilog-AMS Integrated with Polynomial Metamodel for an OP-AMP

Verilog-AMS Integrated with Polynomial Metamodel for a Memristor Oscillator -- Verilog-AMS Integrated with Parasitic-Aware Metamodel -- Kriging-Based Metamodeling -- Theory -- Generation -- Simple Kriging Metamodeling of a Clamped Bitline Sense Amplifier -- Ordinary Kriging Metamodeling of a Sense Amplifier -- Universal Kriging Metamodeling of a Phase-Locked Loop -- Neural Network-Based Metamodeling -- Theory -- Generation -- Neural Network Metamodel of PLL Components -- Intelligent Verilog-AMS -- Kriging Bootstrapped Training for Neural Network Metamodeling -- Ultrafast Process Variations Analysis Using Metamodels -- Kriging-Metamodel-Based Process Variation Analysis of a PLL -- Neural Network Metamodel-Based Process Variation Analysis of a PLL -- Kriging-Trained Neural Network-Based Process Variation Analysis of a PLL

Polynomial-Metamodel-Based Ultrafast Design Optimization -- Polynomial-Metamodel-Based Optimization of a Ring Oscillator -- Polynomial-Metamodel-Based Optimization of a PLL -- Polynomial-Metamodel-Based Optimization of an OP-AMP -- Neural Network Metamodel-Based Ultrafast Design Optimization -- Neural Network Metamodel-Based Optimization of an OP-AMP -- Neural Network Metamodel-Based Variability-Aware Optimization of a PLL -- Kriging Metamodel-Based Ultrafast Design Optimization -- Simple Kriging Metamodel-Based Optimization of a Thermal Sensor -- Ordinary Kriging Metamodel-Based Optimization of a Sense Amplifier -- Questions -- References.